The present invention relates, in general, to metallization for semiconductor devices, and more particularly, to a homogeneous alloy metallization that exhibits reduced stress voiding.
Semiconductor devices use metallization to provide interconnections between devices formed on integrated circuits. Experts predict that performance limits of future integrated circuits will be determined by the performance of the device interconnections. Commonly, metallization schemes use aluminum and aluminum-copper alloys. One problem with aluminum-copper alloy is that stress voids form in metal lines and vias. Stress voids are small areas where metal is missing from the metal line or via. Stress voids reduce the cross-sectional area of the metal line causing increased current density in the metal line during device operation. Because high current density negatively affects reliability of the metal line, the stress voids limit long term reliability of the devices.
One method of controlling stress voids is to use a titanium-tungsten (TiW) alloy barrier layer beneath the metallization. Thin titanium-tungsten alloy cap layers formed on top of the metallization layer also control stress voiding. One problem with these TiW layers is that they require additional deposition steps, increasing processing cost for the semiconductor devices. Also, separate TiW layers increase equipment costs and cycle time for metallization processing. Moreover, sputter deposition of the TiW layers results in high levels of particulate contamination of the semiconductor device. TiW layers are subject to corrosion during reactive ion etching. Finally, titanium in the TiW alloy can interdiffuse into the aluminum-copper metallization during temperature cycling, resulting in increased resistivity.
What is needed is a metallization scheme for semiconductor devices which reduces stress voids without increasing cost, lowering reliability, or substantially increasing resistivity of the metallization.